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rev 1.2 12/15 copyright ? 2015 by si licon laboratories si53102-a1/a2/a3 si53102-a1/a2/a3 pci-e xpress g en 1, g en 2, g en 3, and g en 4 1:2 f an - out c lock b uffer features applications description si53102-a1/a2/a3 is a family of high-performance 1:2 pcie fan output buffers. this low-additive -jitter clock buffer fam ily is compliant to pcie gen 1, gen 2, gen 3, and gen 4 specifications. the ultra-small footprint (1.4x1.6 mm) and industry-leading low power consumption make the si53102-a1/a2/a3 the ideal clock solution for consumer and embedded applications. measuring pcie clock jitte r is quick and easy with the silicon labs pcie clock jitter tool . download it for free at www.silabs.com/pcie- learningcenter . functional block diagram ? pci-express gen 1, gen 2, gen 3, and gen 4 common clock compliant ? two low-power pcie clock outputs ? supports serial-ata (sata) at 100 mhz ? no termination resistors required for differential clocks ? 2.5 v or 3.3 v power supply ? spread spectrum tolerant ? extended temperature: ?40 to 85 c ? small package 8-pin tdfn (1.4x1.6 mm) ? for pcie gen 1: si53102-a1 ? for pcie gen 2: SI53102-A2 ? for pcie gen 3/4: si53102-a3 ? network attached storage ? multi-function printer ? wireless access point ? server/storage diffin diffin diff2 diff1 vdd vss patents pending ordering information: see page 11 pin assignments 8 7 6 5 1 2 3 4 vss diff2 diff2 diff1 diff1 vdd diffin diffin
si53102-a1/a2/a3 2 rev 1.2
si53102-a1/a2/a3 rev 1.2 3 t able of c ontents table of contents page 1. electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. test and measurement setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3. recommended design guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6. package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7. pcb land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
si53102-a1/a2/a3 4 rev 1.2 1. electrical specifications table 1. recommended operating conditions parameter symbol test condition min typ max unit supply voltage (3.3 v supply) v dd 3.3 v 10% 2.97 3.3 3.63 v supply voltage (2.5 v supply) v dd 2.5 v 10% 2.25 2.5 2.75 v table 2. dc electrical specifications parameter symbol test condition min typ max unit operating voltage (vdd = 3.3 v) v dd 3.3 v 10% 2.97 3.30 3.63 v operating voltage (vdd = 2.5 v) v dd 2.5 v 10% 2.25 2.5 2.75 v operating supply current i dd full active ? ? 12 ma input pin capacitance c in input pin capacitance ? 3 5 pf output pin capacitance c out output pin capacitance ? ? 5 pf
si53102-a1/a2/a3 rev 1.2 5 table 3. ac electrical specifications parameter symbol condition min typ max unit diffin at 0.7 v input frequency fin 10 100 175 mhz diffin and diffin rising/falling slew rate t r / t f single ended measurement: v ol = 0.175 to v oh = 0.525 v (averaged) 0.6 ? 4 v/ns differential input high voltage v ih 150 ? ? mv differential input low voltage v il ? ? ?150 mv crossing point voltage at 0.7 v swing v ox single-ended measurement 250 ? 550 mv vcross variation over all edges ? v ox single-ended measurement ? ? 140 mv differential ringback voltage v rb ?100 ? 100 mv time before ringback allowed t stable 500 ? ? ps absolute maximum input voltage v max ?1.15v absolute minimum input voltage v min ?0.3 ? ? v diffin and diffin duty cycle t dc measured at crossing point v ox 45 ? 55 % rise/fall matching t rfm determined as a fraction of 2x(t r ? t f )/(t r + t f ) ?? 20 % diff clocks duty cycle t dc measured at crossing point v ox 45 ? 55 % output skew t skew measured at 0 v differential ? ? 100 ps frequency accuracy f acc all output clocks ? ? 100 ppm slew rate t r/f2 measured differentially from 150 mv 0.6 ? 4.0 v/ns pcie gen 1 pk-pk additive jitter pk- pk gen1 pcie gen 1 si53102-a1 ?? 10 ps pcie gen 2 additive phase jitter rms gen2 10 khz < f < 1.5 mhz, SI53102-A2 ? ? 0.50 ps pcie gen 2 additive phase jitter rms gen2 1.5 mhz < f < nyquist, SI53102-A2 ? ? 0.50 ps pcie gen 3 additive phase jitter rms gen3 includes pll bw 2?4 mhz, cdr = 10 mhz, si53102-a3 ? ? 0.20 ps pcie gen 4 additive phase jitter rms gen4 pcie gen 4 ? ? 0.20 ps crossing point voltage at 0.7 v swing v ox 300 ? 550 mv enable/disable and setup clock stabilization from powerup t stable power up to first output ? ? 3.0 ms notes: 1. visit www.pcisig.com for complete pcie specifications. 2. gen 4 specifications based on the pci-ex press base specification 4.0 rev. 0.5. 3. download the silicon labs pcie clock jitter tool at www.silabs.com/pcie-learningcenter .
si53102-a1/a2/a3 6 rev 1.2 table 4. thermal conditions parameter symbol condition min typ max unit temperature, storage t s non-functional ?65 150 c temperature, operating ambient t a functional ?40 85 c temperature, junction t j functional ? 150 c dissipation, junction to case ? jc jedec (jesd 51) ? 38.3 c/w dissipation, junction to ambient ? ja jedec (jesd 51) ? 90.4 c/w table 5. absolute maximum conditions parameter symbol cond ition min typ max unit main supply voltage v dd_3.3v ?4.6v input voltage v in relative to v ss ?0.5 4.6 v dc esd protection (human body model) esd hbm jedec (jesd 22-a114) 2000 ? v flammability rating ul-94 ul (class) v?0 note: while using multiple power supplies, the voltage on any i nput or i/o pin cannot exceed the power pin during powerup. power supply sequencing is not required .
si53102-a1/a2/a3 rev 1.2 7 2. test and measurement setup figures 1 through 3 show the test load conf iguration for the differential clock signals. figure 1. 0.7 v differential load configuration the outputs from this device can also support lvds, lvpecl, or cml differential signaling levels using alternative termination. for recommendations on how to achieve th is, see ?an781: alternativ e output termination for si5213x, si5214x, si5121x, an d si5315x pcie clock generato r and buffer families? at www.silabs.com . figure 2. differential measurement for differential output signals (ac parameters measurement) measurement point 2pf 50 ? measurement point 2pf 50 ? l1 l1 = 5" out+ out- l1
si53102-a1/a2/a3 8 rev 1.2 figure 3. single-ended measurement for differential output signals (ac parameters measurement)
si53102-a1/a2/a3 rev 1.2 9 3. recommended design guideline figure 4. recommended application schematic 3.3v / 2.5v 4.7uf 0.1uf fb vdd si53102 note: fb specifications: dc resistance 0.1?0.3 ? impedance at 100 mhz > 1000 ?
si53102-a1/a2/a3 10 rev 1.2 4. pin descriptions figure 5. 8-pin tdfn table 6. si53102-ax-gm 8-pin tdfn descriptions pin # name type description 1 diffin o, dif 0.7 v, 100 mhz differentials clock input 2 diffin o, dif 0.7 v, 100 mhz differentials clock input 3 diff1 o, dif 0.7 v, 100 mhz differential clock output 4 diff1 o, dif 0.7 v, 100 mhz differential clock output 5gnd gnd ground 6 diff2 o, dif 0.7 v, 100 mhz differential clock output 7 diff2 o, dif 0.7 v, 100 mhz differential clock output 8vdd pwr 2.5 v or 3.3 v power supply 8 7 6 5 1 2 3 4 vss diff2 diff2 diff1 diff1 vdd diffin diffin
si53102-a1/a2/a3 rev 1.2 11 5. ordering guide part number package type temperature si53102-a1-gm 8-pin tdfn extended, ?40 to 85 ? c si53102-a1-gmr 8-pin tdfn?tape and reel extended, ?40 to 85 ? c SI53102-A2-gm 8-pin tdfn extended, ?40 to 85 ? c SI53102-A2-gmr 8-pin tdfn?tape and reel extended, ?40 to 85 ? c si53102-a3-gm 8-pin tdfn extended, ?40 to 85 ? c si53102-a3-gmr 8-pin tdfn?tape and reel extended, ?40 to 85 ? c
si53102-a1/a2/a3 12 rev 1.2 6. package outlines figure 6. 8-pin tdfn package drawing table 7. package diagram dimensions dimension min nom max a 0.70 0.75 0.80 a1 0.00 0.02 0.05 a3 0.20 ref. b 0.15 0.20 0.25 d 1.60 bsc d2 1.00 1.05 1.10 e 0.40 bsc e 1.40 bsc e2 0.20 0.25 0.30 l 0.30 0.35 0.40 aaa 0.10 bbb 0.10 ccc 0.10 ddd 0.07 eee 0.08 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
si53102-a1/a2/a3 rev 1.2 13 7. pcb land pattern figure 7. si53102 8-pin tdfn land pattern table 8. si53102 8-pin land pattern dimensions dimension mm c1.40 e0.40 x1 0.75 y1 0.20 x2 0.25 y2 1.10 notes: general 1. all dimensions shown are in millimeters (mm). 2. this land pattern design is based on the ipc-7351 guidelines. 3. all dimensions shown are at maximu m material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. solder mask design 4. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 5. a stainless steel, laser-cut and elec tro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. the stencil thickness should be 0.125 mm (5 mils). 7. the ratio of stencil aperture to land pad size should be 1:1 for all pads. card assembly 8. a no-clean, type-3 solder paste is recommended. 9. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. ?
si53102-a1/a2/a3 14 rev 1.2 d ocument c hange l ist revision 0.4 to revision 1.0 ? updated table 3 on page 5. ?? updated input frequency min and max specs. ? updated "2. test and measurement setup" on page 7. ?? added text and reference to an781. revision 1.0 to revision 1.1 ? moved ?3. recommended design guideline? to page 9. ? corrected figure 5 title on page 10. ? corrected table 6 title on page 10. ? corrected figure 6 title on page 12. ? added "7. pcb land pattern" on page 13. revision 1.1 to revision 1.2 ? updated features on page 1. ? updated description on page 1. ? updated specs in table 3, ?ac electrical specifications,? on page 5.
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